Title :
Dynamic-biased capacitor-free NMOS LDO
Author :
Giustolisi, G. ; Palumbo, Gaetano
Author_Institution :
Dipt. di Ing. Elettr. Elettron. e dei Sist., Univ. degli Studi di Catania, Catania, Italy
Abstract :
A low-voltage low drop-out (LDO) voltage regulator is proposed. It is based on an NMOS output stage and exploits dynamic biasing for obtaining low-voltage (1.2 V) and low drop-out (200 mV) features. It does not require any external compensation capacitor and is able to deliver 50 mA with capacitive loads up to 10 nF. The circuit topology is discussed and experimental results are given.
Keywords :
MOS integrated circuits; electric potential; network topology; voltage regulators; NMOS output stage; circuit topology; external compensation capacitor; low-voltage low drop-out voltage regulator; voltage 1.2 mV;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2009.1220
