Charge Domain Interlace Scan Implementation in a CMOS Image Sensor

This paper presents the first CMOS image sensor which implements a charge domain interlacing principle to improve the signal-to-noise ratio (SNR) under equal exposure condition (integration time and light intensity). Inspired by the shared amplifier pixel structure, a novel pixel is designed to fit the charge domain interlacing principle, which works in field integration and frame integration mode. The designed image sensor is implemented in TSMC 0.18 μm CIS technology. This CMOS image sensor also contains a programmable universal image sensor peripheral circuit, allowing this sensor also to support normal progressive scan. By comparing the performances of the sensor working in charge domain interlacing and in the progressive scan, the chip measurement results prove that under the same exposure condition, the light response of the charge domain interlacing is twice that of the progressive scan. The SNR performance can be increased by 6 dB in low light level conditions.