Impact of NBTI/PBTI on SRAM Stability Degradation

Author

Cheng, Binjie ; Brown, Andrew R. ; Asenov, Asen

Author_Institution

Sch. of Eng., Univ. of Glasgow, Glasgow, UK

Volume

32

Issue

6

fYear

2011

fDate

6/1/2011 12:00:00 AM

Firstpage

740

Lastpage

742

Abstract

We investigate the impact of negative-bias temperature instability (NBTI) on the degradation of the static noise margin (SNM) and write noise margin (WNM) of a SRAM cell. This is based on the quantitative simulation of the statistical impact of NBTI on p-MOSFETs corresponding to a 45-nm low-power technology generation. Due to the increasing importance of positive-bias temperature instability (PBTI) of n-MOSFETs with the introduction of high-/v/metal gate stacks, we also explore the additional impact of PBTI on statistical SNM and WNM degradation behavior. The results indicate that NBTI-only induced SNM and WNM degradations follow different evolutionary patterns compared to the impact of simultaneous NBTI and PBTI degradation, and high distribution moment information is required for the reconstruction of noise margin distributions.

Keywords

MOSFET; SRAM chips; high-k dielectric thin films; low-power electronics; NBTI-PBTI; SRAM stability degradation; high distribution moment information; high-k-metal gate stacks; low-power technology generation; n-MOSFET; negative-bias temperature instability; noise margin distributions; p-MOSFET; positive-bias temperature instability; size 45 nm; static noise margin; write noise margin; Degradation; Logic gates; MOSFET circuits; Metals; Noise; Random access memory; Reliability; Reliability; SRAM; static noise margin (SNM); statistical variability (SV); write noise margin (WNM);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2011.2136316

Filename

5766705