Title :
Path planning using hardware time delays
Author_Institution :
Dept. of Comput. Sci., Zurich Univ., Switzerland
fDate :
6/1/1999 12:00:00 AM
Abstract :
The computation of shortest paths as a basic task in robotics can be accomplished by graph-searching algorithms. Attempts have been made to accelerate a part of these algorithms-the computation of potential vectors-using fine-grained parallel hardware. As shown in this paper, the complexity of digital path-planning circuits can be enormously reduced, if distances are encoded by hardware time delays
Keywords :
computational complexity; delays; minimisation; mobile robots; parallel processing; path planning; robot programming; complexity; digital path-planning circuits; fine-grained parallel hardware; graph-searching algorithms; hardware time delays; potential vectors; robotics; shortest path computation; Acceleration; Concurrent computing; Costs; Delay effects; Hardware; Integrated circuit interconnections; Logic gates; Parallel processing; Path planning; Robots;
Journal_Title :
Robotics and Automation, IEEE Transactions on
