Title :
Low-complexity bit-parallel systolic architecture for computing AB 2+C in a class of finite field GF(2m)
Author :
Lee, Chiou-Yng ; Lu, Erl-Huei ; Sun, Lir-Fang
Author_Institution :
Dept. of Electr. Eng., Chang Gung Univ., Chung Li, Taiwan
fDate :
5/1/2001 12:00:00 AM
Abstract :
An algorithm for computing AB2+C over a finite field GF(2m) is presented using the properties of the irreducible all one polynomial of degree m. Based on the algorithm, a parallel-in parallel-out systolic multiplier is proposed. The architecture of the multiplier is very simple, regular, modular, and exhibits very low latency and propagation delay. Therefore, it is suitable for very large scale integration implementation of cryptosystems
Keywords :
VLSI; computational complexity; cryptography; digital signal processing chips; multiplying circuits; polynomials; systolic arrays; all one polynomial; bit-parallel systolic architecture; cryptosystems; finite field; latency; modular architecture; parallel-in parallel-out systolic multiplier; propagation delay; very large scale integration; Arithmetic; Computer architecture; Cryptography; Galois fields; Hardware; Polynomials; Propagation delay; Signal processing algorithms; Sun; Very large scale integration;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
