DocumentCode :
1516115
Title :
Verifying the FM9801 microarchitecture
Author :
Hunt, Warren A., Jr. ; Sawada, Jun
Author_Institution :
Lab. of Res., IBM Corp., Austin, TX, USA
Volume :
19
Issue :
3
fYear :
1999
Firstpage :
47
Lastpage :
55
Abstract :
Hardware verification accounts for a considerable portion of the costs in the microprocessor design process. Traditionally designers have verified microprocessor designs using simulation techniques that help find most design faults. However, simulation never guarantees the correct operation of the final product. Some design faults are very difficult to detect by simulation; they may slip through the verification process into manufactured chips, raising costs. We believe that verification costs can be reduced by the judicious application of formal methods, which should lower the overall costs of design
Keywords :
computer architecture; digital simulation; formal verification; logic design; FM9801 microarchitecture verification; design faults; hardware verification; microprocessor design process; simulation techniques; Circuit testing; Clocks; Formal verification; Hardware design languages; Instruction sets; Logic devices; Mathematical model; Microarchitecture; Microprocessors; Signal design;
fLanguage :
English
Journal_Title :
Micro, IEEE
Publisher :
ieee
ISSN :
0272-1732
Type :
jour
DOI :
10.1109/40.768503
Filename :
768503
Link To Document :
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