Low switching noise and load-adaptive output buffer design techniques

Author

Jou, Shyh-Jye ; Kuo, Shu-Hua ; Chiu, Jui-Ta ; Lin, Tin-Hao

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

Volume

36

Issue

8

fYear

2001

fDate

8/1/2001 12:00:00 AM

Firstpage

1239

Lastpage

1249

Abstract

Switching noise due to di/dt is becoming severe as technology states, resulting in a great need for noise-suppression techniques. Several techniques to reduce the switching noise caused by output buffers in CMOS chips are described. An ac/dc output buffer design technique is proposed that includes an innovative feedback mechanism to reduce switching noise and output signal ringing while at the same time maintains timing and dc current requirement. Also, a technique of adaptively separated simultaneous switching noise is proposed that can increase the number of simultaneously switching outputs per V_DD and GND pair. Measurement results show that the ac/dc buffer can reduce the output ringing by 2.5× and VDD/GND line bounce by 1.7× and the ASN can double the number of simultaneous switching outputs under the same conditions as compared to the weighted and distributed buffer

Keywords

CMOS logic circuits; SPICE; buffer circuits; circuit feedback; driver circuits; integrated circuit design; integrated circuit noise; AC/DC output buffer design technique; CMOS chips; HSPICE simulation; feedback mechanism; load-adaptive output buffer design; low switching noise; noise-suppression; output signal ringing; parasitic inductance; voltage bounce; CMOS technology; Delay effects; Driver circuits; Inductance; Integrated circuit noise; Noise reduction; Parasitic capacitance; Switches; Switching circuits; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.938374

Filename

938374