Title :
A low-power direct digital synthesizer using a self-adjusting phase-interpolation technique
Author :
Nosaka, Hideyuki ; Yamaguchi, Yo ; Yamagishi, Akihiro ; Fukuyama, Hiroyuki ; Muraguchi, Masahiro
Author_Institution :
Photonics Labs., NTT Corp., Kanagawa, Japan
fDate :
8/1/2001 12:00:00 AM
Abstract :
A complete direct digital synthesizer (DDS) using a self-adjusting phase-interpolation technique is fabricated using 0.35-μm CMOS process technology. A self-adjusting delay generator reduces the periodic jitter in the most significant bit (MSB) of the accumulator in this DDS. To improve the spectral performance, a method of spurious signal reduction that uses offset current sources (OCSs) is newly adopted in the delay generator. Test results confirm that the delay generator produces highly accurate delay timing without the need to adjust circuit constants. The measured spurious free dynamic range (SFDR) is 62 dBc for a dc to 10-MHz output and the power consumption of the complete DDS is 39.2 mW at a 100-MHz clock rate
Keywords :
CMOS integrated circuits; direct digital synthesis; interpolation; low-power electronics; 0.35 micron; 100 MHz; 39.2 mW; CMOS process technology; delay generator; low-power direct digital synthesizer; offset current source; periodic jitter; power consumption; self-adjusting phase interpolation; spurious free dynamic range; CMOS process; CMOS technology; Circuit testing; Delay; Dynamic range; Jitter; Power measurement; Signal generators; Synthesizers; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
