Advanced hardware architecture for soft decoding Reed-Solomon codes

Soft decision decoding of Reed-Solomon codes improves decoding performance considerably in comparison to hard decision decoding. In this paper, we propose an advanced architecture based on information set decoding for processing soft information. The architecture features efficient order-2 reprocessing and handling of multiple information sets. Complexity and performance of the architecture for the widely used RS(255,239) are evaluated on a Virtex 5 FPGA. A communications gain of 1.3 dB is achieved, which outperforms to our best knowledge all other state-of-the-art implementations by more than 0.5 dB.