DocumentCode
1517431
Title
Efficient Retiming of Multirate DSP Algorithms
Author
Zhu, Xue-Yang ; Basten, Twan ; Geilen, Marc ; Stuijk, Sander
Author_Institution
State Key Lab. of Comput. Sci., Inst. of Software, Beijing, China
Volume
31
Issue
6
fYear
2012
fDate
6/1/2012 12:00:00 AM
Firstpage
831
Lastpage
844
Abstract
Multirate digital signal processing (DSP) algorithms are often modeled with synchronous dataflow graphs (SDFGs). A lower iteration period implies a faster execution of a DSP algorithm. Retiming is a simple but efficient graph transformation technique for performance optimization, which can decrease the iteration period without affecting functionality. In this paper, we deal with two problems: feasible retiming-retiming a SDFG to meet a given iteration period constraint, and optimal retiming-retiming a SDFG to achieve the smallest iteration period. We present a novel algorithm for feasible retiming and based on that one, a new algorithm for optimal retiming, and prove their correctness. Both methods work directly on SDFGs, without explicitly converting them to their equivalent homogeneous SDFGs. Experimental results show that our methods give a significant improvement compared to the earlier methods.
Keywords
digital signal processing chips; graph theory; logic design; SDFG retiming; graph transformation technique; iteration period constraint; multirate DSP algorithm; multirate digital signal processing algorithms; optimal retiming; performance optimization; synchronous dataflow graph; Computational modeling; Delay; Digital signal processing; IP networks; Schedules; Signal processing algorithms; Vectors; Iteration period; multirate digital signal processing (DSP); optimization; retiming; synchronous dataflow graphs;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2011.2182352
Filename
6200447
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