DocumentCode
1517773
Title
Considerations for Ultimate CMOS Scaling
Author
Kuhn, Kelin J.
Author_Institution
Intel Corp., Hillsboro, OR, USA
Volume
59
Issue
7
fYear
2012
fDate
7/1/2012 12:00:00 AM
Firstpage
1813
Lastpage
1828
Abstract
This review paper explores considerations for ultimate CMOS transistor scaling. Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted. Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results.
Keywords
CMOS integrated circuits; MOSFET; nanowires; silicon-on-insulator; CMOS transistor scaling; FinFET; nanowire device architecture; omega-FET; pi-gate; thin silicon-on-insulator; transistor architecture; trigate; CMOS integrated circuits; Capacitance; Electrostatics; Logic gates; Materials; Metals; Resistance; Complementary metal-oxide semiconductor (CMOS); FinFET; mobility; nanowire; silicon on insulator (SOI); strain;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2012.2193129
Filename
6200837
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