Simulation Study of Performance for a 20-nm Gate Length In $_{\bf 0.53}$ Ga $_{\bf 0.47}$ As Impl

An nMOSFET for the future high mobility dual-channel CMOS based on anew In_0.53Ga_0.47As implant free quantum well architecture is optimized to achieve low leakage and high on-current. Various aspects of its performance are evaluated using the ensemble Monte Carlo technique, calibrated drift-diffusion simulations, and non-equilibrium Green´s functions technique. The numerical investigations demonstrate that the implant-free quantum-well nMOSFET has a better electrostatic integrity (a subthreshold slope of ~80 mV/dec and a drain induced barrier lowering of ~40 mV/V) and less sensitivity to the interface states density than the implanted III-V surface channel architectures. We predict a very large drive current with a swift onset for the device with δ-doping on the backside of the channel. For the device variant without δ-doping, we observe the on-current reduction by about 30% and a large influence of thickness of lateral spacers (access regions) on the drive current due to the lack of carriers. Finally, the decrease in the channel thickness results in the increase of a higher valleys contribution into the total current from 4% to 25% when the channel is shrunk from to 2 nm.