DocumentCode :
1518230
Title :
Pattern-Mining for Behavioral Synthesis
Author :
Cong, Jason ; Huang, Hui ; Jiang, Wei
Author_Institution :
Dept. of Comput. Sci., Univ. of California, Los Angeles, CA, USA
Volume :
30
Issue :
6
fYear :
2011
fDate :
6/1/2011 12:00:00 AM
Firstpage :
939
Lastpage :
944
Abstract :
Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the regularity in applications for design optimizations. In this letter, we present a general pattern-based behavior synthesis framework which can efficiently extract similar structures in programs. Our approach is very scalable in benefit of advanced pruning techniques. The similarity of structures is captured by a mismatch-tolerant metric: the graph edit distance. The graph edit distance can naturally capture different program variations such as bit-width, structure, and port variations. In addition, we further our approach to handle control-intensive applications, and this leads to more opportunities for optimization. Our algorithm uses a feature-based filtering approach for fast pruning, and a graph similarity metric called the generalized edit distance for measuring variations in control-data flow graphs. Furthermore, we apply our pattern-based synthesis system to the resource optimization problem in behavioral synthesis. Considering knowledge of discovered patterns, the resource binding step can intelligently generate the data-path to reduce interconnect costs. Experiments show that our approach can, on average, reduce the total area by about 20% with 7% latency overhead with our pattern techniques on the Xilinx Virtex-4 field-programmable gate arrays, compared to the traditional behavioral synthesis flow.
Keywords :
data flow graphs; field programmable gate arrays; Xilinx Virtex-4 field-programmable gate array; behavioral synthesis flow; bitwidth structure; control-data flow graph; feature-based filtering approach; generalized edit distance; graph edit distance; graph similarity metric; handle control-intensive application; mismatch-tolerant metric; pattern-based behavior synthesis framework; pattern-mining; port variation; pruning technique; resource binding step; resource optimization problem; Field programmable gate arrays; Harmonic analysis; Microwave FET integrated circuits; Pattern matching; Sensitivity; Area optimization; behavioral synthesis; edit distance; pattern mining;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2011.2106370
Filename :
5768132
Link To Document :
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