Title :
The fast tracker processor for hadron collider triggers
Author :
Annovi, A. ; Bagliesi, M.G. ; Bardi, A. ; Carosi, R. ; Dell´Orso, M. ; D´Onofrio, M. ; Giannetti, P. ; Iannaccone, G. ; Morsani, F. ; Pietri, M. ; Varotro, G.
Author_Institution :
INFN, Pisa, Italy
fDate :
6/1/2001 12:00:00 AM
Abstract :
Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times.
Keywords :
data acquisition; field programmable gate arrays; nuclear electronics; pipeline processing; trigger circuits; CMS experiment; LHC; fast track reconstruction; fast tracker processor; hadron collider triggers; level-1 trigger; level-2 trigger logic; pipelined highly parallel processor; secondary vertices; Collision mitigation; Data acquisition; Detectors; Field programmable gate arrays; Large Hadron Collider; Logic; Pattern recognition; Pipeline processing; Roads; Trajectory;
Journal_Title :
Nuclear Science, IEEE Transactions on
