DocumentCode
1518765
Title
Simple low power analogue MOS voltage adder
Author
Al-Nsour, M. ; Abdel-Aty-Zohdy, H.S.
Author_Institution
Dept. of Electr. & Syst. Eng., Oakland Univ., Rochester, MI, USA
Volume
35
Issue
7
fYear
1999
fDate
4/1/1999 12:00:00 AM
Firstpage
552
Lastpage
553
Abstract
A simple, low power, NMOS analogue voltage adder, suitable for VLSI implementation is presented. It is based on the inherent square law of MOS transistors operating in saturation mode. Using a 3.3 V source, the circuit´s input voltage range is ±3 V, with an error less than 0.3% compared with the ideal sum of the inputs. The power consumption is <0.5 mW and THD <-36 dB for the full range of operation
Keywords
MOS analogue integrated circuits; VLSI; adders; analogue processing circuits; low-power electronics; 0.5 mW; 3.3 V; MOS transistors; NMOS analogue voltage adder; VLSI implementation; low power analogue MOS adder; power consumption; saturation mode; square law;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19990414
Filename
769477
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