• DocumentCode
    1518784
  • Title

    Low-power logic synthesis algorithm using multiple partitioning under delay constraints

  • Author

    Choi, Ick-Sung ; Hwang, Sun-Young

  • Author_Institution
    Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea
  • Volume
    35
  • Issue
    7
  • fYear
    1999
  • fDate
    4/1/1999 12:00:00 AM
  • Firstpage
    558
  • Lastpage
    560
  • Abstract
    A synthesis algorithm is proposed for the design of a low power combinational circuit under delay constraints. The algorithm partitions a given circuit into several subcircuits, such that only one selected subcircuit is activated at a time, hence reducing unnecessary signal transitions. Experimental results show that the proposed algorithm is efficient for designing low power CMOS digital circuits
  • Keywords
    CMOS logic circuits; circuit CAD; combinational circuits; delays; integrated circuit design; logic CAD; logic partitioning; low-power electronics; simulated annealing; delay constraints; low power CMOS digital circuit design; low power combinational circuit; low-power logic synthesis algorithm; multiple partitioning;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19990409
  • Filename
    769481
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1518784