Phase Noise Issues With FPGA-Embedded DLLs and PLLs in HEP Applications

Author

Aloisio, A. ; Giordano, R. ; Izzo, V.

Author_Institution

INFN Sezione di Napoli, Naples, Italy

Volume

58

Issue

4

fYear

2011

Firstpage

1664

Lastpage

1671

Abstract

Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) are available as embedded hard-macros in the latest Field Programmable Gate Arrays (FPGAs). Their main features are clock phase de-skewing, frequency multiplication and division. Moreover, the availability of PLLs allows the user to perform jitter filtering too. The clock signal at the output of a DLL or a PLL has a phase noise, which has to be taken into account in timing sensitive applications, such as analog-to-digital conversion, time measurements or high-speed serial links.

Keywords

data acquisition; delay lock loops; field programmable gate arrays; high energy physics instrumentation computing; nuclear electronics; phase locked loops; phase noise; Data Acquisition systems; HEP applications; Large Hadron Collider; Xilinx Virtex FPGA; analog-to-digital conversion; clock multiplication; clock network de-skew; clock phase de-skewing; clock signal; delay locked loops; field programmable gate arrays; frequency 40 MHz; frequency 60 MHz; frequency division; frequency multiplication; high energy physics; high-speed serial links; jitter filtering; phase locked loops; phase noise issues; time measurements; Bandwidth; Clocks; Field programmable gate arrays; Jitter; Phase locked loops; Phase noise; DLL; FPGA; PLL; jitter; phase noise;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2011.2143727

Filename

5770191