Multiloop High-Power-Supply-Rejection Quadrature Ring Oscillator

This paper presents a source-follower-delay-cell, multiloop ring oscillator that provides power-supply isolation. The main contributions of this work are a source-follower-based delay cell with a multiloop ring structure achieving improved supply rejection, a design-oriented analysis of the proposed structure to facilitate its use, and a layout technique allowing straightforward mask design for the multiloop oscillator. The oscillator also features differential control voltages to allow rejection of common-mode control and supply noise. The oscillator was fabricated in a UMC 90-nm CMOS pure logic process with no analog components (regular VT), and the minimum measured incremental supply sensitivity is 0.003 [%-change f_osc^/%-change V_DD], which is more than 20 dB better than that of a conventional CMOS-delay-cell quadrature oscillator fabricated on the same test chip. The oscillator´s measured tuning range is 0.63-8.1 GHz. Over the tuning range, the phase noise varies from - 106 to - 88 dBc/Hz at 10-MHz offset, and the power consumption ranges from 7 to 26 mW from a 1-V supply. The measured mean quadrature accuracy performance is within -1.5° to +2.25° error including board parasitics without any trimming/tuning across the oscillator´s frequency range.