• DocumentCode
    1519151
  • Title

    Comments on "Breaking the 2n-bit carry-propagation barrier in residue to binary conversion for the [2/sup n/-1, 2/sup n/, 2/sup n/+1] moduli set" and author\´s reply

  • Author

    Mohan, P.V.A. ; Premkumar, A.B. ; Bhardwaj, Manish

  • Author_Institution
    Transmission R&D, I.T.I. Ltd., Bangalore, India
  • Volume
    48
  • Issue
    8
  • fYear
    2001
  • Firstpage
    1031
  • Abstract
    In the above paper [see ibid., vol. 45, p. 998-1002, 1998] Bharadwaj et al, have suggested two changes for Piestrak´s technique [1995]. It may be recalled that the first stage in Piestrak´s converter contains two levels of 2n bit carry-save adders each comprising of 2n full adders since four inputs need to be added. Interestingly, Dhurkadas´s modification [1998] of Pieshak´ s technique reduces the four addends to three, thus needing one level of carry-save adders only. We would like to make some observations on this modification. The authors´ reply is included.
  • Keywords
    adders; carry logic; residue number systems; Dhurkadas´s modification; Piestrak´s technique; carry-propagation barrier; carry-save adders; residue to binary conversion; Added delay; Adders; Circuits; DH-HEMTs; Delay effects; Dynamic range; Hardware; Research and development; Signal processing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1057-7122
  • Type

    jour

  • DOI
    10.1109/81.940195
  • Filename
    940195