Reconfigurable on-chip antenna arrays for multi-chip RF data transmission

Summary form only given. Multicore computer architectures with upwards of 100 processor cores on a single chip promise unprecedented enhancement of computational performance. There are many key performance issues in computing on multicore systems that do not exist in single core computers or even computers with a few cores. Maximum computational performance, such as ideal load balancing and low latency, can only be achieved with efficient data transfers between cores. The full promise of multicore systems cannot be achieved unless efficient (both in energy and time) communications between cores is realized. In an multicore computer architecture with hundreds cores, physical connections will severely restrict system performance due to slowed data transfer, excessive power consumption and required redundancy for broken data links.