Title :
ASMD with duty cycle correction scheme for high-speed DRAM
Author :
Jang, Seong-Jin ; Jun, Young-Hyun ; Lee, Jae-Goo ; Bai-Sun Kon
Author_Institution :
Sch. of Electr. & Comput. Eng, SungKyunKwan Univ., Suwon, South Korea
fDate :
8/2/2001 12:00:00 AM
Abstract :
An analogue synchronous mirror delay with duty cycle-correction scheme (ASMDCC), to improve the data transmission performance between DRAM and system, is proposed. The ASMDCC achieves duty cycle correction and clock synchronisation at once within two clock cycles, by using a half value current source. The simulation results show the duty cycle of the internal clock is stabilised with less than ±100 ps deviation from 50% for the wide duty cycle range
Keywords :
DRAM chips; analogue processing circuits; circuit simulation; clocks; delays; high-speed integrated circuits; synchronisation; ASMD; analogue synchronous mirror delay; clock synchronisation; dual edge triggering systems; duty cycle-correction scheme; half value current source; high-speed DRAM; internal clock duty cycle stabilisation; simulation results; wide duty cycle range;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010717
