Effect of switch resistance on the SC integrator settling time

Author

Chilakapari, U. ; Fiez, Terri S.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA

Volume

46

Issue

6

fYear

1999

fDate

6/1/1999 12:00:00 AM

Firstpage

810

Lastpage

816

Abstract

Using general feedback theory, a model is developed for the switched-capacitor integrator. This model is then used to analyze the effects of sampling and feedback switch resistances on the integrator settling time. If the frequency corresponding to the sampling time constant is less than five times the frequency of the second pole of the amplifier, the integrator settling time will be degraded. The feedback switch resistance has little effect on the integrator settling time for switch resistances up to 50 kΩ

Keywords

circuit feedback; electric resistance; equivalent circuits; integrating circuits; network analysis; signal sampling; switched capacitor networks; SC integrator settling time; amplifier second pole; general feedback theory; sampling effects; sampling time constant; switch resistance effect; switched-capacitor integrator model; Bandwidth; Capacitance; Capacitors; Degradation; Frequency; Operational amplifiers; Output feedback; Sampling methods; Signal processing; Switches;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.769789

Filename

769789