DocumentCode
15221
Title
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation
Author
Endo, Sho ; Yang Li ; Homma, Naofumi ; Sakiyama, Kazuo ; Ohta, Kazuo ; Fujimoto, Daisuke ; Nagata, Makoto ; Katashita, Toshihiro ; Danger, Jean-Luc ; Aoki, Takafumi
Author_Institution
Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
Volume
23
Issue
8
fYear
2015
fDate
Aug. 2015
Firstpage
1429
Lastpage
1438
Abstract
In this paper, we present an efficient countermeasure against fault sensitivity analysis (FSA) based on configurable delay blocks (CDBs). FSA is a new type of fault attack, which exploits the relationship between fault sensitivity (FS) and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against differential fault analysis (DFA), such as redundancy calculation, masked and-or, and wave dynamic differential logic. The proposed countermeasure can thwart both DFA and FSA attacks based on setup time violation faults. The proposed ideas are to use a CDB as a time base for detection and to combine the technique with Li´s countermeasure concept that removes the dependency between FSs and secret data. The postmanufacture configuration of the CDBs allows minimization of the overhead in operating frequency that comes from manufacture variability. In this paper, we also present an implementation of the proposed countermeasure in application-specified integrated circuit, and describe its configuration method. We then investigate the hardware overhead of the proposed countermeasure for an advanced encryption standard processor and demonstrate its validity through an experiment.
Keywords
application specific integrated circuits; cryptography; logic circuits; logic design; sensitivity analysis; silicon; CDB; DFA attacks; FSA attacks; Si; application-specified integrated circuit; configurable delay blocks; cryptographic modules; differential fault analysis; encryption standard processor; fault attack; fault sensitivity analysis; hardware overhead; redundancy calculation; silicon-level countermeasure; wave dynamic differential logic; Circuit faults; Clocks; Cryptography; Delays; Registers; Sensitivity analysis; Advanced encryption standard (AES); application-specified integrated circuit (ASIC) implementation; fault sensitivity analysis (FSA); side-channel analysis;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2014.2339892
Filename
6872596
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