Title :
Parasitic transistor effects in CMOS VLSI
Author :
Chen, John Y. ; Lewis, Alan G.
Author_Institution :
Xerox, Palo Alto, CA, USA
fDate :
5/1/1988 12:00:00 AM
Abstract :
Parasitic field-effect transistor (FETs) and bipolar junction transistors (BJTs) in a CMOS circuit are described, along with their interactions with each other and their effect on circuit performance. The results are considered to be useful for setting up design rules between n-channel and p-channel active transistors in CMOS IC layout. Novel parasitic transistors associated with next-generation VLSI technologies, such as trench isolation and silicon-on-insulator, are discussed briefly.<>
Keywords :
CMOS integrated circuits; VLSI; CMOS VLSI; SOI; active transistors; bipolar junction transistors; circuit performance; field-effect transistor; next-generation VLSI; parasitic transistors; trench isolation; Bipolar transistor circuits; CMOS integrated circuits; CMOS technology; Doping; FETs; Integrated circuit layout; Petroleum; Silicon; Threshold voltage; Very large scale integration;
Journal_Title :
Circuits and Devices Magazine, IEEE
