Title :
Four-Terminal-Relay Body-Biasing Schemes for Complementary Logic Circuits
Author :
Nathanael, Rhesa ; Pott, Vincent ; Kam, Hei ; Jeon, Jaeseok ; Alon, Elad ; Liu, Tsu-Jae King
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California at Berkeley, Berkeley, CA, USA
Abstract :
Four-terminal-relay inverter circuit characteristics are investigated. To achieve maximum noise margin and zero crowbar current while allowing for relay-to-relay variations, the optimal biasing scheme provides for switching that is symmetric about VDD/2 with minimum hysteresis and no possibility of both the pull-down and pull-up devices being on simultaneously.
Keywords :
invertors; logic circuits; complementary logic circuits; four-terminal-relay body-biasing schemes; four-terminal-relay inverter circuit characteristics; relay-to-relay variations; Microelectromechanical systems (MEMS); nanoelectromechanical systems (NEMS); relay logic;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2010.2050133
