DocumentCode :
1522422
Title :
Tilt angle effect on DC and AC performance of Halo PMOS
Author :
Su, Jlong-Guang ; Wong, Shyh-Chyl ; Lee, Da-Yuan ; Huang, Chi-Tsung ; Tsui, Bing-Yue
Author_Institution :
Institute of Electronics Engineering, National Chiao-Tung University, IIsinchu, Taiwan, R.O.C.
fYear :
1996
Firstpage :
1
Lastpage :
31
Abstract :
Halo structure is usually adopted in deep submicron MOS devices for off-state leakage current reduction. Tilt angle of the Halo implant determines dopant distribution which gives anti-punchthrough operation. In this paper, we investigate the impact of tile angle on both DC and AC performance of Halo PMOS device via 2-D simulations. For DC performance, it is found that same conduction current is obtained for all tilt angles at same leakage current level. This performance equivalence can be traced back to a self compensation between body factor and source resistance, and implies that low tilt angle should be adopted for Halo devices, as it gives small threshold voltage and thus high noise margin. For AC performance, it is found that at same leakage current level, all tilt angles give same gate-to-drain capacitance and that lower tilt angle gives smaller drain-to-bulk junction capacitance.
Keywords :
Capacitance; Immune system; Implants; Junctions; Leakage current; Performance evaluation; Semiconductor process modeling;
fLanguage :
English
Journal_Title :
Technology Computer Aided Design TCAD, Journal of
Publisher :
ieee
ISSN :
1097-2102
Type :
jour
DOI :
10.1109/TCAD.1996.6449173
Filename :
6449173
Link To Document :
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