DocumentCode :
1522451
Title :
A fast nonenumerative automatic test pattern generator for path delay faults
Author :
Tragoudas, S. ; Karayiannis, D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Volume :
18
Issue :
7
fYear :
1999
fDate :
7/1/1999 12:00:00 AM
Firstpage :
1050
Lastpage :
1057
Abstract :
This paper presents a nonenumerative automatic test pattern generator for robustly testable path delay faults. In contrast to earlier work by I. Pomeranz, et al. (see IEEE Trans. Computer-Aided Design, vol. 14, p. 1505-15, Dec. 1995), the pattern generator takes into consideration the conditions for robust propagation while sensitizing sets of paths. This increases the probability of testing them robustly with a single test. Novel algorithms are described which identify sets that contain many such potentially compatible paths. The number of detected faults is estimated using a simple and fast method. The approach compares favorably to that of Pomeranz et al. in both fault detection and time performance
Keywords :
automatic test pattern generation; delays; digital integrated circuits; fault location; integrated circuit testing; logic testing; probability; automatic test pattern generator; fast nonenumerative ATPG; fault detection performance; path delay faults; probability; robust propagation; robustly testable faults; time performance; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Delay effects; Electrical fault detection; Fault detection; Propagation delay; Robustness; Test pattern generators;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.771185
Filename :
771185
Link To Document :
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