Junction capacitance reduction due to self-aligned pocket implantation in elevated source/drain NMOSFETs

Author

Miura, Naruhisa ; Abe, Yuji ; Sughihar, K. ; Oishi, Toshiyuki ; Furukawa, Taisuke ; Nakahata, Takumi ; Shiozawa, Katsuomi ; Maruno, Shigemitsu ; Tokuda, Yasunori

Author_Institution

Adv. Technol. R&D Center, Mitsubishi Electr. Corp., Hyogo, Japan

Volume

48

Issue

9

fYear

2001

fDate

9/1/2001 12:00:00 AM

Firstpage

1969

Lastpage

1974

Abstract

A new advantage of an elevated source/drain (S/D) configuration to improve MOSFET characteristics is presented. By adopting pocket implantation into an elevated S/D structure which was formed by Si selective epitaxial growth and gate sidewall removal, we demonstrate that the parasitic junction capacitance as well as the junction leakage was significantly reduced for an NMOSFET while maintaining its good short channel characteristics. These successful results are attributed to the modification of the boron impurity profile in the deep S/D regions. The capacitance reduction rate, furthermore, was more remarkable as the pocket dose was further increased. This means that the present self-aligned pocket implantation is very promising for future MOSFETs with a very short gate length, where high pocket dosage will be required to suppress the short channel effect

Keywords

MOSFET; capacitance; ion implantation; NMOSFET; Si:B; boron impurity profile; elevated source/drain structure; gate sidewall removal; junction leakage; parasitic junction capacitance; self-aligned pocket implantation; short channel effect; silicon selective epitaxial growth; Boron; Doping; Epitaxial growth; Fabrication; Impurities; Ion implantation; MOS devices; MOSFET circuits; Parasitic capacitance; Silicides;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.944184

Filename

944184