Title :
Instruction buffering to reduce power in processors for signal processing
Author :
Bajwa, Raminer S. ; Hiraki, Mitsuru ; Kojima, Hirotsugu ; Gorny, Douglas J. ; Nitta, Kenichi ; Shridhar, Avadhani ; Seki, Koichi ; Sasaki, Katsuro
Author_Institution :
Semicond. Res. Lab., Hitachi America Ltd., Brisbane, CA, USA
Abstract :
Power consumption analyzes of embedded processors indicate that a significant amount of power is consumed in accessing memory and in the control path. Based on this, and on the runtime characteristics of signal processing applications, we advocate the use of instruction buffering as a power-saving technique for processors for signal processing and multimedia applications. Two approaches, a decoded instruction buffer (DIB) and a decoded instruction cache, are considered. Performance improvements in representative applications in speech processing such as, the vector sum excited linear prediction (VSELP), linear prediction coding coefficient computation (LPC), and two-dimensional 2-D 8/spl times/8 DCT which is used in image compression, are provided. The reduction in power obtained is between between 25 and 30%.
Keywords :
data compression; digital signal processing chips; discrete cosine transforms; image coding; linear predictive coding; multimedia computing; real-time systems; speech processing; decoded instruction buffer; decoded instruction cache; embedded processors; image compression; instruction buffering; linear prediction coding coefficient computation; multimedia applications; power consumption; power-saving technique; runtime characteristics; speech processing; two-dimensional 2D 8/spl times/8 DCT; vector sum excited linear prediction; Decoding; Discrete cosine transforms; Energy consumption; Image coding; Linear predictive coding; Runtime; Signal processing; Speech processing; Two dimensional displays; Vectors;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
