DocumentCode
1523219
Title
Phase accumulator synthesis algorithm for DDS applications
Author
Romero-Troncoso, R.de J. ; Verdad, G. Espinosa-Flores-
Author_Institution
Guanajuato Univ., Puebla, Mexico
Volume
35
Issue
10
fYear
1999
fDate
5/13/1999 12:00:00 AM
Firstpage
770
Lastpage
772
Abstract
An algorithm for area-speed optimisation in phase accumulator synthesis is presented. Digital direct synthesis (DDS) requires an efficient phase accumulator as its main functional block. However, fast phase accumulators are very area-demanding and the tradeoff between area and speed is very critical. The approach can be used for the optimisation and synthesis of phase accumulators in FPGAs and ASICs
Keywords
application specific integrated circuits; circuit CAD; circuit optimisation; direct digital synthesis; field programmable gate arrays; flip-flops; high level synthesis; integrated circuit design; pipeline processing; ASICs; DDS applications; FPGAs; area-speed optimisation; digital direct synthesis; phase accumulator synthesis algorithm;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19990539
Filename
771406
Link To Document