Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology

Author

Bertrand, Géraldine ; Delage, Christelle ; Bafleur, Marise ; Nolhier, Nicolas ; Dorkel, Jean-Marie ; Nguyen, Quang ; Mauran, Nicolas ; Trémouilles, David ; Perdu, Philippe

Author_Institution

Lab. d´´Autom. et d´´Anal. des Syst., CNRS, Toulouse, France

Volume

36

Issue

9

fYear

2001

fDate

9/1/2001 12:00:00 AM

Firstpage

1373

Lastpage

1381

Abstract

A thorough analysis of the physical mechanisms involved in a vertical grounded-base n-p-n bipolar transistor (VGBNPN) under electrostatic discharge (ESD) stress is first carried out by using two-dimensional (2-D) device simulation, transmission line pulse measurement (TLP) and photoemission experiments. This analysis is used to account for the unexpected low value of the VGBNPN snapback holding voltage under TLP stress. A compact model based on a new avalanche formulation resulting from the exact resolution of the ionization integral is therefore proposed

Keywords

bipolar transistors; electrostatic discharge; power integrated circuits; protection; semiconductor device models; ESD protection; avalanche multiplication; compact model; impact ionization; photoemission; smart power technology; snapback holding voltage; transmission line pulse measurement; two-dimensional device simulation; vertical grounded-base n-p-n bipolar transistor; Analytical models; Bipolar transistors; Electrostatic analysis; Electrostatic discharge; Ionization; Photoelectricity; Pulse measurements; Stress; Two dimensional displays; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.944666

Filename

944666