Title :
Improved adiabatic pseudo-domino logic family
Author :
Lau, K.T. ; Liu, Frank
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst.
fDate :
12/4/1997 12:00:00 AM
Abstract :
An improved input-isolation structure for APDL (adiabatic pseudo-domino logic) is proposed. The proposed circuit, IAPDL (improved APDL), provides a higher frequency performance in excess of 1 GHz with simple clock supplies. It is more compact compared with T-APDL (transmission gate-interfaced APDL) and the power dissipation is generally about half that of APDL. HSPICE simulations were performed and the results indicate that a reduction of up to 75% in power dissipation can be achieved compared to conventional CMOS
Keywords :
CMOS logic circuits; logic design; 0.8 micron; HSPICE simulations; adiabatic pseudo-domino logic family; clock supplies; improved APDL; input-isolation structure; n-well CMOS process; power dissipation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19971454
