Cooling as a possible way to extend the usability of IDDQ testing

A reduction of the V_DD voltage, and thus the threshold voltage, in submicrometre CMOS circuits, results in an increase in the subthreshold current of the transistors and, consequently, in an increase in the overall quiescent current. This effect prohibits the use of I_DDQ testing. Based on experimental investigation into the subthreshold characteristics of deep submicrometre transistors, the authors propose a cooling of the circuit under test as a method to reduce these difficulties