SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

Author

Mukhopadhyay, Saibal ; Rao, Rahul M. ; Kim, Jae-Joon ; Chuang, Ching-Te

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

19

Issue

1

fYear

2011

Firstpage

24

Lastpage

32

Abstract

Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45-nm PD/SOI technology show a 10³X reduction in the Write-failure probability with the proposed method.

Keywords

CMOS memory circuits; SRAM chips; coupled circuits; low-power electronics; CMOS technology; SRAM cell; SRAM write-ability improvement; capacitive coupling; size 100 nm; transient negative bit-line voltage; CMOS technology; Degradation; Delay; Inverters; Mathematical analysis; Partial discharges; Probability; Random access memory; Read-write memory; Voltage control; Capacitive coupling; SRAM; variation; write-ability;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2009.2029114

Filename

5299101