Triple-bit method for power estimation of nonlinear digital circuits in FPGAs

Power consumption of many of the digital signal processing systems available is nonlinear. Signal distribution at the multiplier output changes significantly with respect to its input signal distributions. Data signals have a large impact on design power, so the multiplier output has to be modelled properly. A model to compute the bit-level switching activity of each multiplier output bit is presented. This model depends on word-level signal statistics and the number of multiplied input signals. It is applied to high-level power estimation of FPGA designs. The relative errors of the presented power model with respect to measured power are four to five times smaller than the errors obtained by using the standard signal model for high-level power estimation.