Interconnect sizing and spacing with consideration of coupling capacitance

Author

Cong, Jason ; He, Lei ; Koh, Cheng-Kok ; Pan, Zhigang David

Author_Institution

Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA

Volume

20

Issue

9

fYear

2001

fDate

9/1/2001 12:00:00 AM

Firstpage

1164

Lastpage

1169

Abstract

This paper studies interconnect sizing and space (ISS) problem with consideration of coupling capacitance for performance optimization of single or multiple critical nets. We introduce the formulation of symmetric and asymmetric wire sizing. We develop efficient bound computation algorithms for ISS optimization and prove their optimality under general interconnect resistance and capacitance models. Our experiments show that our algorithms are very effective and obtain significant performance improvement compared to previous wire-sizing/spacing algorithms

Keywords

VLSI; capacitance; circuit optimisation; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; ISS optimization algorithm; capacitance model; coupling capacitance; critical net; deep submicron VLSI design; interconnect sizing; interconnect spacing; resistance model; Capacitance; Circuit optimization; Delay effects; Design optimization; Helium; Integrated circuit interconnections; Lagrangian functions; Routing; Very large scale integration; Wire;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.945311

Filename

945311