Title :
On the complexity of gate duplication
Author :
Srivastava, Ankur ; Kastner, Ryan ; Sarrafzadh, M.
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fDate :
9/1/2001 12:00:00 AM
Abstract :
In this paper, we show that both the global and local gate duplication problems for delay optimization are NP-complete under certain delay models
Keywords :
VLSI; circuit complexity; circuit optimisation; delays; integrated circuit design; integrated circuit modelling; NP-complete problem; VLSI design; circuit complexity; delay model; delay optimization; global gate duplication; local gate duplication; Algorithm design and analysis; Capacitance; Circuits; Computer science; Delay; Equations; Load modeling; Optimization methods; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
