Title :
A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop
Author :
Chuang, Chi-Nan ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A 20-MHz to 3-GHz wide-range multiphase delay-locked loop (DLL) has been realized in 90-nm CMOS technology. The proposed delay cell extends the operation frequency range. A scaling circuit is adopted to lower the large delay gain when the frequency of the input clock is low. The core area of this DLL is 0.005 mm2. The measured power consumption values are 0.4 and 3.6 mW for input clocks of 20 MHz and 3 GHz, respectively. The measured peak-to-peak and root-mean-square jitters are 2.3 and 16 ps at 3 GHz, respectively.
Keywords :
CMOS integrated circuits; delay lock loops; jitter; scaling circuits; CMOS technology; delay cell; frequency 20 MHz to 3 GHz; power 0.4 mW to 3.6 mW; scaling circuit; size 90 nm; wide-range multiphase delay-locked loop; Delay cell; delay-locked loop (DLL); multiphase; wide range;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2009.2032477
