Title :
A tabular method for guard strengthening, symmetrization, and operator reduction for Martin´s asynchronous design methodology
Author :
Tabrizi, Nozar ; Liebelt, Michael J. ; Eshraghian, Kamran
Author_Institution :
Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
fDate :
9/1/1997 12:00:00 AM
Abstract :
We introduce a tabular method to perform the last two of the four phases of Martin´s compilation process for asynchronous circuit design. The method is then demonstrated with three examples, illustrating that our systematic method is very straight forward, flexible, and convenient to apply, and, hence, it lends itself to automatic compilation
Keywords :
asynchronous circuits; logic design; sequential circuits; Martin´s asynchronous design; asynchronous circuit design; asynchronous sequential circuits; automatic compilation; delay insensitive circuits; formal program transformation; guard strengthening; guarded commands; operator reduction; self-timed logic; signal transition graphs; speed independent circuits; symmetrization; tabular method; Asynchronous circuits; Circuit synthesis; Clocks; Delay; Design methodology; Driver circuits; Logic design; Production; Sequential circuits; Signal synthesis;
Journal_Title :
Computers, IEEE Transactions on
