Title :
Logic synthesis of a PLL phase frequency detector
Author :
Piguet, C. ; von Kaenel, V.
Author_Institution :
Centre Suisse d´´Electronique et de Microtechnique SA, Neuchatel, Switzerland
fDate :
11/1/1997 12:00:00 AM
Abstract :
The design of the phase frequency detector of the phase-locked loop (PLL) of the Strongarm microprocessor has been designed according to an asynchronous design methodology based on negative gates. This methodology is based on a CMOS gate delay model which takes into account the delays of input inverters. The resulting phase frequency detector presents a better performance than the conventional circuits used generally in phase-locked loops
Keywords :
CMOS logic circuits; asynchronous circuits; delays; detector circuits; digital phase locked loops; frequency-domain synthesis; invertors; logic design; logic gates; microprocessor chips; signal detection; CMOS gate delay model; Strongarm microprocessor; asynchronous design methodology; input inverter delay; logic synthesis; negative gates; performance; phase frequency detector; phase-locked loop;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
DOI :
10.1049/ip-cdt:19971495
