Title :
Bit-serial multiplication in GF(2m) using irreducible all-one polynomials
Author :
Fenn, S.T.J. ; Parker, M.G. ; Benaissa, M. ; Taylor, D.
Author_Institution :
Dept. of Electr. & Electron. Eng., Huddersfield Univ., UK
fDate :
11/1/1997 12:00:00 AM
Abstract :
Two architectures for carrying out bit-serial multiplication in the GF(2m) finite field are presented where the defining irreducible polynomial for the field is an all-one polynomial. The multipliers presented have low hardware requirements, regular structures and are therefore suitable for VLSI implementation
Keywords :
Reed-Solomon codes; VLSI; cryptography; digital arithmetic; polynomials; GF(2m) finite field; Reed-Solomon codes; VLSI implementation; bit-serial multiplication; cryptography; hardware requirements; irreducible all-one polynomials; multipliers; regular structures;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
DOI :
10.1049/ip-cdt:19971586
