A model for the high-level description and simulation of VLSI networks

An applicative state transition (AST) model for the description and analysis of synchronous and asynchronous VLSI networks at the top levels of abstraction is presented. The model, which uses two powerful paradigms that provide an elegant, fast method for the high-level description and simulation of VLSI networks, explicitly represents the flow of information through a network. This is done by embedding the AST concept into the theory of Petri nets and using Petri net theory to define the communication protocol between nodes. It allows the description of both synchronous and asynchronous designs from the level of abstract functional or algorithmic behaviour down to the register-transfer level. In design descriptions, the model logically separates state, function, and function control, increasing the clearness of the description and simplifying the development and application of silicon compilers. As an application the design of a simple priority queue as both a real-time systolic (synchronous) system and a real-time wavefront (asynchronous) system is explored. This example demonstrates the capability of the AST graph model to handle loops in the design. The model has been embedded in an interactive design system called HIFI (Hierarchical Interactive Flowgraph Integration).<>