Title :
Low-leakage germanium-seeded laterally-crystallized single-grain 100-nm TFTs for vertical integration applications
Author :
Subramanian, Vivek ; Toita, Masato ; Ibrahim, Nabeel R. ; Souri, Shukri J. ; Saraswat, Krishna C.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
fDate :
7/1/1999 12:00:00 AM
Abstract :
We report on 100-nm channel-length thin-film transistors (TFTs) that are fabricated using germanium-seeded lateral crystallization of amorphous silicon. Germanium seeding allows the fabrication of devices with control over grain boundary location. Its effectiveness improves with reduced device geometry, allowing "single-grain" device fabrication. In the first application of this technology to deep submicron devices, we report on 100-nm devices having excellent performance compared to conventional TFTs, which have randomly located grains. Devices have on-off ratio >10/sup 6/ and subthreshold slope of 107 mV/decade, attesting to the suitability of germanium-seeding for the fabrication of high-performance TFTs, suitable for use in vertically integrated three-dimensional (3-D) circuits.
Keywords :
crystallisation; elemental semiconductors; germanium; grain boundaries; leakage currents; silicon; thin film transistors; 100 nm; Ge; Si; deep submicron device; fabrication; germanium seeded lateral crystallization; grain boundary; leakage current; on-off ratio; polysilicon TFT; single-grain device; subthreshold slope; thin film transistor; three-dimensional circuit; vertical integration; Amorphous silicon; Circuits; Crystallization; Etching; Fabrication; Geometry; Germanium alloys; Grain boundaries; MOS devices; Thin film transistors;
Journal_Title :
Electron Device Letters, IEEE
