Title :
Cached DRAM for ILP processor memory access latency reduction
Author :
Zhang, Zhao ; Zhu, Zhichun ; Zhang, Xiaodong
Author_Institution :
Coll. of William & Mary, Williamsburg, VA, USA
Abstract :
Cached DRAM adds a small cache onto a DRAM chip to reduce average DRAM access latency. The authors compare cached DRAM with other advanced DRAM techniques for reducing memory access latency in instruction-level-parallelism processors
Keywords :
DRAM chips; cache storage; memory architecture; parallel architectures; DRAM access latency; ILP; cached DRAM; instruction-level-parallelism processors; latency reduction; processor memory access latency; Bandwidth; Capacitors; Computer aided instruction; Concurrent computing; Delay; Impedance; Interleaved codes; Parallel processing; Random access memory; SDRAM;
Journal_Title :
Micro, IEEE
