Title :
Evaluating the use of register queues in software pipelined loops
Author :
Tyson, Gary S. ; Smelyanskiy, Mikhail ; Davidson, Edward S.
Author_Institution :
University of Michigan
fDate :
8/1/2001 12:00:00 AM
Keywords :
Computer architecture; Degradation; Delay; Hardware; Kernel; Optimizing compilers; Pipeline processing; Registers; Throughput; VLIW;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.2001.947006
