• DocumentCode
    1525462
  • Title

    Physically-based threshold voltage determination for MOSFET´s of all gate lengths

  • Author

    Tsuno, Morikazu ; Suga, Masato ; Tanaka, Masayasu ; Shibahara, Kentaro ; Miura-Mattausch, Mitiko ; Hirose, Masataka

  • Author_Institution
    Matsushita Electron. Corp., Kyoto, Japan
  • Volume
    46
  • Issue
    7
  • fYear
    1999
  • fDate
    7/1/1999 12:00:00 AM
  • Firstpage
    1429
  • Lastpage
    1434
  • Abstract
    A reliable method to determine the threshold voltage Vth for MOSFETs with gate length down to the sub-0.1 μm region is proposed. The method determines Vth by linear extrapolation of the transconductance gm to zero and is therefore named “GMLE method”. To understand the physical meaning of the method and to prove its reliability for different technologies 2-D simulation was applied. The results reveal that determined Vth values always meet the threshold condition, i.e., the onset of inversion layer buildup
  • Keywords
    MOSFET; extrapolation; semiconductor device models; 0.1 micron; 2D simulation; GMLE method; MOSFET; gate length; inversion layer; linear extrapolation; physical model; threshold voltage; transconductance; Associate members; Capacitance measurement; Current measurement; Data mining; Extrapolation; Helium; Length measurement; MOSFET circuits; Threshold voltage; Transconductance;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.772487
  • Filename
    772487
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1525462