A 130-nm channel length partially depleted SOI CMOS-technology

Author

Pindl, Stephan ; Berthold, Jörg ; Huttner, Thomas ; Reif, Stefan ; Schumann, Dirk ; von Philisborn, H.

Author_Institution

Corp. Technol., Siemens AG, Munich, Germany

Volume

46

Issue

7

fYear

1999

fDate

7/1/1999 12:00:00 AM

Firstpage

1562

Lastpage

1566

Abstract

A partially depleted silicon-on-insulator (PDSOI) CMOS technology employing pocket implantation and a self-aligned titanium silicidation with an effective gate length of 0.13 μm has been developed. An advanced mesa isolation process is used to suppress corner devices. A clear improvement of the device performance due to the novel isolation process is shown. Good transfer characteristics with a steep subthreshold slope and an excellent roll-off of threshold voltage is obtained for both nMOS and pMOS devices down to effective gate lengths of 0.13 μm. A 10 k transistor circuit which is mostly combinatoric (carry select adder circuit) has been realized and characterized as a performance test circuit with an effective gate length of 0.18 μm and shows high performance and low power consumption compared to an optimized 0.18 μm effective gate length bulk technology with similar processing

Keywords

CMOS integrated circuits; isolation technology; low-power electronics; silicon-on-insulator; 0.13 nm; Si; TiSi₂; carry select adder circuit; low power consumption; mesa isolation process; nMOS devices; pMOS devices; partially depleted SOI CMOS-technology; pocket implantation; self-aligned Ti silicidation; subthreshold slope; threshold voltage roll-off; transfer characteristics; Adders; CMOS technology; Circuit testing; Combinatorial mathematics; Isolation technology; MOS devices; Silicidation; Silicon on insulator technology; Threshold voltage; Titanium;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.772511

Filename

772511