A 130-nm channel length partially depleted SOI CMOS-technology

A partially depleted silicon-on-insulator (PDSOI) CMOS technology employing pocket implantation and a self-aligned titanium silicidation with an effective gate length of 0.13 μm has been developed. An advanced mesa isolation process is used to suppress corner devices. A clear improvement of the device performance due to the novel isolation process is shown. Good transfer characteristics with a steep subthreshold slope and an excellent roll-off of threshold voltage is obtained for both nMOS and pMOS devices down to effective gate lengths of 0.13 μm. A 10 k transistor circuit which is mostly combinatoric (carry select adder circuit) has been realized and characterized as a performance test circuit with an effective gate length of 0.18 μm and shows high performance and low power consumption compared to an optimized 0.18 μm effective gate length bulk technology with similar processing