DocumentCode
1525802
Title
0.9 V to 5 V Bidirectional Mixed-Voltage I/O Buffer With an ESD Protection Output Stage
Author
Wang, Chua-Chin ; Kuo, Ron-Chi ; Liu, Jen-Wei
Author_Institution
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Volume
57
Issue
8
fYear
2010
Firstpage
612
Lastpage
616
Abstract
A 0.9 V to 5 V (0.9/1.2/1.8/2.5/3.3/5 V) mixed-voltage I/O buffer with NMOS clamping technique is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit a sub-3 × VDD voltage-level signal without gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a floating N-well circuit. The maximum data rate is measured at 66 MHz for 5/3.3/2.5/1.8/1.2/0.9 V with an equivalent probe capacitive load of 10 pF.
Keywords
MOS integrated circuits; buffer circuits; electrostatic discharge; ESD protection output stage; NMOS clamping technique; VDD voltage-level signal; bidirectional mixed-voltage I-O buffer; capacitance 10 pF; dynamic gate bias generator; floating N-well circuit; frequency 66 MHz; gate drive voltages; voltage 0.9 V to 5 V; Floating N-well circuit; I/O buffer; gate-oxide reliability; mixed-voltage-tolerant;
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2010.2050941
Filename
5497114
Link To Document