Title :
Parallel multiplication using fast sorting networks
Author_Institution :
Sanders, Lockheed Martin Co., Nashua, NH, USA
fDate :
6/1/1999 12:00:00 AM
Abstract :
A recent paper describes the use of Svoboda´s binary counter in the construction of fast parallel multipliers. The resulting approach was shown to be faster than the conventional Dadda multiplier when the wordlength N was small. Unfortunately, the growth in the number of gates of that method was O(N3) and the speed was O(N). In this paper, Batcher´s bitonic sorting network and other efficient networks replace the Svoboda counter. The asymptotic growth rate in gates of these new methods is O(N2 log2 N), and the speed is O(log2 N)
Keywords :
counting circuits; digital arithmetic; sorting; bitonic sorting network; fast parallel multipliers; fast sorting networks; parallel multiplication; Adders; Counting circuits; Hardware; Propagation delay; Signal processing; Sorting;
Journal_Title :
Computers, IEEE Transactions on