Title :
Parametric wafer map visualization
Abstract :
The semiconductor industry widely exploits bin wafer maps and their spatial information for process monitoring and yield enhancement. However, the bin wafer maps´ underlying parameters are even more sensitive and informative. In this article, I describe the design of an interactive wafer map visualization tool and its implementation using Tcl/Tk. More importantly, I demonstrate how one could use the resulting color wafer maps to uncover subtle manufacturing process patterns, variations and trends that are otherwise extremely difficult to detect and discover
Keywords :
colour graphics; data visualisation; electronic engineering computing; engineering graphics; integrated circuit technology; integrated circuit yield; Tcl/Tk implementation; bin wafer maps; color wafer maps; interactive visualization tool; manufacturing process patterns; manufacturing process trends; manufacturing process variations; parametric wafer map visualization; process monitoring; semiconductor industry; spatial information; yield enhancement; Automatic control; Data visualization; Displays; Fabrication; Failure analysis; Graphical user interfaces; Mice; Semiconductor device modeling; Sun; Workstations;
Journal_Title :
Computer Graphics and Applications, IEEE
